Semiconductor device

ABSTRACT

A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region. A field oxide film surrounds the first region in a plan view. A metal interconnect situated over a field oxide film. The metal interconnect formed of a metal having an electric resistivity at 25° C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Further, the metal interconnect is repeatedly provided spirally in a direction along the edges of the first region. Further, the metal interconnect is electrically connected at the innermost circumference with the drain region, and is connected at the outermost circumference to the source region or a ground potential.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2014-116435 filed onJun. 5, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device which provides atechnique applicable, for example, to power devices.

In the power devices, a lateral reduced surface field (RESURF)transistor is sometimes used as described, for example, in JapaneseUnexamined Patent Application Publication No. 2012-39029. Suchtransistor has a field oxide film between a drain region and a sourceregion. In the transistor described above, a high voltage is appliedbetween the drain region and the source region. The field oxide film isprovided for improving a withstand voltage between the drain region andthe source region.

Japanese Unexamined Patent Application Publication No. 2010-16153describes an LDMOS (Laterally-Diffused Metal Oxide Semiconductor) as thepower device. In Japanese Unexamined Patent Application Publication No.2010-16153, LDMOS and CMOS (Complementary MOS) are hybridized over anidentical semiconductor substrate.

Japanese Unexamined Patent Application Publication No.Hei07(1995)-263547 describes that a PSG (Phospho Silicate Glass) filmand a silicon nitride film are stacked in this order over an aluminuminterconnect.

SUMMARY

In the transistor exemplified as an RESURF transistor and used for thepower device, a high voltage is applied between a drain region and asource region. In this case, an electric field is sometimes concentratedto a portion of a region overriding the drain region and the sourceregion. The concentration of the electric field sometimes gives anundesired effect on the characteristics of the transistor. Then, thepresent inventors have studied a new structure for suppressing theconcentration of the electric field. Other subjects and novel featureswill become apparent in view of the descriptions of the presentspecification and the appended drawings.

According to a preferred embodiment, a drain region is formed in a firstregion and a source region is formed in a second region. A fieldinsulation film surrounds the first region in a plan view. A metalinterconnect is situated over the field insulation film. The metalinterconnect is formed of a metal having an electric resistivity at 25°C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Further, the metalinterconnect is provided repeatedly while being turned-back or spirallyin the direction along the edges of the first region. The metalinterconnect is electrically connected at the innermost circumferencewith the drain region and electrically connected at the outermostcircumference with the source region or a ground potential.

According to another embodiment, the metal interconnect is situated byway of an interlayer dielectric film over the field insulation film. Afirst metal electrode is situated on the side of the first region incontrast to the metal interconnect in a plan view and covers theinterlayer dielectric film. The first metal electrode is electricallyconnected with the drain region. In the same manner, a second metalelectrode is situated on the side of the second region in contrast tothe metal interconnect in the plan view and covers the interlayerdielectric film. The second metal electrode is electrically connectedwith the source region. A barrier metal film is formed along the bottomof the first metal electrode and the bottom of the second metalelectrode. The metal interconnect is formed of a material identical withthat of the barrier metal film.

According to another embodiment, an anti-reflection film covers thefirst metal electrode and the second metal electrode described above.The anti-reflection film is a metal film. The metal interconnect isformed of a material identical with that of the anti-reflection film.

According to the embodiment, concentration of the electric field in aregion overriding the drain region and the source region can besuppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a configuration of a semiconductordevice according to a first embodiment;

FIG. 2 is a cross sectional view along line A-A′ in FIG. 1;

FIG. 3 is a cross sectional view illustrating a method of manufacturingthe semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 4 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 5 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 6 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 7 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 8 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 9 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 10 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 11 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 1 and FIG. 2;

FIG. 12 is a cross sectional view illustrating the configuration of asemiconductor device according to second embodiment;

FIG. 13 is a cross sectional view illustrating a method of manufacturingthe semiconductor device illustrated in FIG. 12;

FIG. 14 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 12;

FIG. 15 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 12;

FIG. 16 is a cross sectional view illustrating the method ofmanufacturing the semiconductor device illustrated in FIG. 12; and

FIG. 17 is a plan view illustrating a configuration of a semiconductordevice according to a modified embodiment.

DETAILED DESCRIPTION

Preferred embodiments of the invention are to be described withreference to the drawings. Throughout the drawings, identicalconstitutional elements carry same reference numerals for whichexplanation is to be omitted optionally.

First Embodiment

FIG. 1 is a plan view illustrating a configuration of a semiconductordevice SD according to a first embodiment. FIG. 2 is a cross sectionalview along line A-A′ in FIG. 1.

As illustrated in FIG. 1, a semiconductor device SD has a first regionRG1, a second region RG2, and a field oxide film FOS (field insulationfilm) in the substrate SUB. In the embodiment illustrated in thedrawing, the field oxide film FOX has a planar rectangular shape havingan opening in the inside. The first region RG1 is situated in theopening. Thus, the first region RG1 is surrounded by the field oxidefilm FOX in a plan view. In the embodiment illustrated in the drawing,the first region RG1 has a planar rectangular shape rounded at thecorners. The second region RG2 is situated by way of the field oxidefilm FOX outside the first region RG1 in the plan view.

A metal interconnect MW is formed over the field oxide film FOX. In theembodiment illustrated in the drawing, the metal interconnect MW isrepeatedly provided spirally in the direction along the edges of thefirst region RG1. The planer configuration of the metal interconnect MWis not restricted to that of the embodiment illustrated in the drawing.For example, the metal interconnect MW may also be repeatedly providedwhile being turned-back in the direction along the edges of the firstregion RG1.

As illustrated in FIG. 2, a semiconductor device SD has a firstconduction type body region PBD, a second conduction type drift regionNDR, and a field oxide film FOX in a substrate SUB. Further, thesemiconductor device SD has a gate electrode GE, a conduction film CF,an interlayer dielectric film ILD, a metal interconnect MW, barriermetal films BM1 and BM2, metal electrodes ME1 and ME2, a protection filmPL, and a cover film CL over the substrate SUB.

The first conduction type and the second conduction type may either be ap-type or an n-type so long as the conduction types are opposite eachother. Description is to be made hereinafter that the first conductiontype is the p-type and the second conduction type is the n-type.

The substrate SUB is, for example, a semiconductor substrate and,specifically, a silicon substrate or an SOI (Silicon on Insulator)substrate. In the embodiment illustrated in the drawing, the conductiontype of the substrate SUB is a first conduction type (p-type). Theconduction type of the substrate SUB may also be the second conductiontype (n-type). In the embodiment illustrated in the drawing, while thefirst conduction type body region PBD and the second conduction typedraft region NDR are formed in the substrate SUB, the structure of thesemiconductor device SD is not restricted to the example illustrated inthe drawing. For example, the first conduction type body region PBD andthe second conduction type drift region NDR may also be formed to anepitaxial layer formed over the substrate SUB.

The first conduction type body region PBD is formed in the second regionRG2. The first conduction type body region PBD includes a source regionSOR and a first conduction type body contact region PBC. The sourceregion SOR is an n⁺ region (second conduction type region). The firstconduction type body contact region PBC is a p⁺ region (first conductiontype region) having the impurity concentration higher than that of thefirst conduction type body region PBD. The source region SOR is situatedon the side of the first region RG1 in contrast to the first conductiontype body region PBD. On the other hand, the first conduction type bodyregion PBD is situated on the side of the second region RG2 in contrastto the the source region SOR.

The second conduction type drift region NDR is situated on the side ofthe second region RG2 in contrast to the first conduction type bodyregion PBD. The second conduction type drift region NDR is situated fromthe first region RG1 to the second region RG2. The second conductiontype drift region NDR includes the field oxide film FOX in the surfacelayer and includes the drain region DRR on the side of the first regionRG1 in contrast to the field oxide film FOX. The drain region DRR is ann⁺ region (second conduction type region) having an impurityconcentration higher than that of the second conduction type driftregion NDR.

The gate electrode GE is situated over the substrate SUB and formed fromthe source region SOR to the field oxide film FOX in a plan view. Thegate electrode GE is formed, for example, of polysilicon. A gateinsulation film GI is situated between the gate electrode GE and thesubstrate SUB. The gate insulation GI is formed, for example, of asilicon oxide film (SiO₂).

The interlayer dielectric film ILD covers the substrate SUB and thefield oxide film FOX. The interlayer dielectric film ILD is formed, forexample, of a silicon oxide film (SiO₂). A source contact SOC and adrain contact DR are formed to the interlayer dielectric film. Thesource contact SOC penetrates the interlayer dielectric film ILD and isconnected with the source region SOR. In the same manner, the draincontact DRC penetrates the interlayer dielectric film ILD and isconnected with the drain region DRR. In the example illustrated in thedrawing, the upper surface of the interlayer dielectric film ILD has ashape reflecting the unevenness from the surface of the substrate SUB tothe surface of the field oxide film FOX. However, the upper surface ofthe interlayer dielectric film ILD may also be flat.

The metal interconnect MW is situated by way of the interlayerdielectric film ILD over the field oxide film FOX. The metalinterconnect MW is formed of a high resistance metal. Specifically, themetal interconnect MW is formed of a metal having an electricresistivity at 25° C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Morespecifically, the metal interconnect MW is formed, for example, oftitanium, titanium nitride, tantalum, or tantalum nitride. However, thematerial of the metal interconnect MW is not restricted to the materialdescribed above. In this embodiment, the metal interconnect MW is astacked film (TiN/Ti) formed by stacking titanium (Ti) and titaniumnitride (TiN) in this order on the side of the interlayer dielectricfilm ILD.

As described above, the metal interconnect MW is repeatedly providedspirally in the direction along the edges of the first region RG1 in aplan view (FIG. 1). Further, the metal interconnect MW is electricallyconnected at the innermost circumference with the drain region DRR andis electrically connected at the outermost circumference to the sourceregion SOR or a ground potential. In this embodiment, a voltage appliedto the drain region DRR is higher than the voltage applied to the sourceregion SOR. In this case, a current flows in the metal interconnect MWfrom the inner circumference (on the side of the drain region DRR) tothe outer circumference (on the side of the source region SOR). In thiscase, potential on the metal interconnect MW gradually decreases fromthe inner circumference to the outer circumference. In this case, theelectric field generated between the inner circumference and the outercircumference of the metal interconnect MW is substantially uniform.

The metal electrode ME1 is situated on the side of the second region RG2in contrast to the metal interconnect MW in a plan view. On the otherhand, the metal electrode ME2 is situated on the side of the firstregion RG1 in contrast to the metal interconnect MW in a plan view. Themetal electrodes ME1 and ME2 cover the interlayer dielectric film ILD.The metal electrode ME1 is formed integrally with the source contact SOCand electrically connected with the source region SOR. On the otherhand, the metal electrode MB2 is formed integrally with the draincontact DRC and electrically connected with the drain region DRR. Themetal electrodes ME1 and ME2 are formed, for example, of aluminum (Al).

The barrier metal film BM1 is formed along the bottom and the lateralside of the source contact SOC and along the bottom of the metalelectrode ME1. On the other hand, the barrier metal BM2 is formed alongthe bottom and the lateral side of the drain contact DPC and the bottomof the metal electrode ME2. The barrier metal films BM1 and BM2 aremetal films for preventing the metal forming the metal electrode ME1(for example, aluminum (Al) from diffusing to the interlayer dielectricfilm ILD or the substrate SUB (for example, the drain region DRR or thesource region SOR). The barrier metal films BM1 and BM2 are formed of amaterial identical with that of the metal interconnect MW. In thisembodiment, each of the barrier metal films BM1 and BM2 is a stackedfilm (TiN/Ti) formed by stacking titanium (Ti) and the titanium nitride(TiN) in this order from the interlayer dielectric film ILD.

A conduction film CF is situated over the substrate SUB, and formed fromthe drain region DRR to the field oxide film FOX in a plan view. Theconduction film CF is formed of a material identical with that of thegate electrode GE (for example, polysilicon). The conduction film CF iselectrically connected by way of a contact (not illustrated) thatpenetrates the metal electrode ME2 and the barrier metal film BM2 withthe metal electrode ME2. In this case, a voltage applied to the drainregion DRR is identical with the voltage applied to the conduction filmCF. Thus, a portion of the conduction film CF riding over the fieldoxide film FOX serves as a field plate for moderating the electric fieldbetween the gate electrode GE and the drain region DRR.

A protection film PL covers the metal electrodes ME1 and ME2, and themetal interconnect MW. Further, in the example illustrated in thedrawing, a cover film CL covers the protection film PL. The protectionfilm PL is an insulation film for protecting, for example, the metalelectrodes ME1 and ME2, and the metal interconnect MW from an externalcircumstance (for example, preventing the metal from oxidation).Specifically, the protection film PL is, for example, a silicon nitridefilm (SiN). On the other hand, the cover film CL is, for example, formedof PSG (Phospho Silicate Glass). Materials for the protection film PLand the cover film CL are not restricted to the examples describedabove.

The gate electrode GE, the metal electrode ME1, and the metal electrodeME2 are connected electrically with a first pad, a second pad, and athird pad (not illustrated) respectively. Such pads are formed, forexample, over the protection film PL and are partially covered by thecover film CL. Then, by applying a voltage to the pads, a drivingvoltage is applied to the gate electrode GE, the source region SOR(metal electrode ME1) and the drain region DRR (metal electrode ME2).

FIG. 3 to FIG. 11 are cross sectional views illustrating a method ofmanufacturing the semiconductor device SD illustrated in FIG. 1 and FIG.2.

First, as illustrated in FIG. 3, a first conduction type body region PBDand a second conduction type drift region NDR are formed to the surfaceof the substrate SUB by implanting ions into the substrate SUB. Then, afield oxide film FOX is formed over the surface of the substrate SUB.The field oxide film FOX is formed, for example, by LOCOS (LocalOxidation of Silicon) or STI (Shallow Trench Isolation). The order forthe steps of forming the first conduction type body region PBD and thesecond conduction type drift region NDR, and the field oxide film FOXmay be reversed. Then, a polysilicon film PS and an insulation film GI1are formed in this order over the substrate SUB and the field oxide filmFOX. The polysilicon film PS is a conduction film that forms the gateelectrode GE and the conduction film CF. The insulation film GI1 is aninsulation film that forms the gate insulation film GI.

Then, as illustrated in FIG. 4, the polysilicon film PS and theinsulation film GI1 are patterned. Thus, a gate electrode GE and aconduction film CF are formed, and a gate insulation film GI is formedbelow the gate electrode GE and the conduction film CF.

Then, as illustrated in FIG. 5, ions are implanted into the substrateSUB, thereby forming a drain region DRR and a source region SOR, andforming the first conduction type body contact region PBC.

Then, as illustrated in FIG. 6, an interlayer dielectric film ILD isformed over the substrate SUB, over the field oxide film FOX, over thegate electrode GE, and over the conduction film CF.

Then, as illustrated in FIG. 7, connection holes CH1 and CH2 are formedin the interlayer dielectric film ILD. The connection holes CH1 and theconnection hole CH2 penetrate the interlayer dielectric film ILD andreach the drain region DRR and the source region SOR respectively. Aswill be detailed later, a drain contact DRC and a source contact SOC areformed to the connection holes CH1 and connection hole CH2,respectively.

Then, as illustrated in FIG. 8, a barrier metal film BM and a metal filmME are stacked in this order over the interlayer dielectric film ILD.Thus, the barrier metal film BM is formed along the bottoms and thelateral sides of the connection holes CH1 and CH2 and the upper surfaceof the interlayer dielectric film ILD. On the other hand, the metal filmME fills the connection holes CH1 and CH2 to form a drain contact DRCand a source contact SOC. Further, the metal film ME is formed by way ofthe barrier metal BM along the upper surface of the interlayerdielectric film ILD. The barrier metal film BM and the metal film ME areformed, for example, by sputtering.

As will be described specifically later, the barrier metal film BM is ametal film that forms barrier metal films BM1 and BM2 and the metalinterconnect MW. The metal film ME is a metal film that forms metalelectrodes ME1 and ME2. In this embodiment, the barrier metal film BM isa stacked film (TiN/Ti) formed by stacking titanium (Ti) and titaniumnitride (TiN) in this order from the side of the interlayer dielectricfilm ILD. On the other hand, metal film ME is formed of aluminum (Al).However, the materials for the barrier metal film BM and the metal filmME are not restricted to those described above.

Then, as illustrated in FIG. 9, the metal film ME is patterned, therebyforming an opening OP in the metal film ME over the field oxide filmFOX. Thus, the metal film ME forms a metal electrode ME1 on the side ofthe second region RG2 in contrast to the opening OP in a plan view, andforms a metal electrode ME2 on the side of the first region RG1 incontrast to the opening OP in the plan view. In this step, the metalfilm ME situated in the region where the opening OP is formed isremoved, for example, by reactive ion etching (RIE).

More specifically, the etching rate of the metal film ME according tothis embodiment is different from that of the barrier metal film BM(particularly, upper surface of the barrier metal film BM). Accordingly,in the step illustrated in the drawing, the metal film ME can be removedselectively in contrast to the barrier metal film BM. However, thesurface layer of the barrier metal film BM is also removed depending onetching conditions. In this case, the thickness of the barrier metalfilm BM in the region where the opening OP is situated is less than thethickness of the barrier metal film BM situated below the metalelectrodes ME1 and ME2.

Then, as illustrated in FIG. 10, the barrier metal film BM situatedinside the opening OP in a plan view is patterned, thereby forming ametal interconnect MW. In this step, the barrier metal film BM to beremoved by patterning is removed, for example, by RIE. When thethickness of the barrier metal film BM in the region where the openingOP is situated is less than the thickness of the barrier metal film BMsituated below the metal electrodes ME1 and ME2 as described above, thethickness of the metal interconnect MW is less than the thickness of thebarrier metal film situated below the metal electrodes ME1 and ME2.

Then, as illustrated in FIG. 11, a protection film PL and a cover filmCL are stacked in this order over the metal electrodes ME1 and ME2 andover the metal interconnect MW. Thus, the semiconductor device SDillustrated in FIG. 1 and FIG. 2 is manufactured.

As described above, according to this embodiment, the metal interconnectMW is formed by way of the interlayer dielectric film ILD over the fieldoxide film FOX. The metal interconnect MW is repeatedly providedspirally in the direction along the edges of the first region RG1 in aplan view. The metal interconnect MW is electrically connected at theinnermost circumference with the drain region DRR and is electricallyconnected at the outermost circumference with the source region or theground potential. Accordingly, when a high voltage is applied to thedrain region DRR and a low voltage is applied to the source region SOR,a substantially uniform electric field is generated between the innercircumference (on the side of the drain region DRR) and the outercircumference (on the side of the source region SOR) of the metalinterconnect MW. Thus, concentration of the electric field to a regionbetween the high voltage side (on the side of the drain region DRR) andthe low voltage side (on the side of the source region SOR) can besuppressed.

Particularly, according to this embodiment, the protection film PL isformed over the metal electrodes ME1 and ME2 and over the metalinterconnect MW. When the protection film PL is a silicon nitride (SiN)film, the metal interconnect MW functions particularly effectively.Specifically, the silicon nitride film (protection film PL) has a lot ofdangling bonds at the upper surface and the upper surface tends toabsorb moisture. Accordingly, negative charges tend to be trapped to theupper surface of the silicon nitride film. Then, when the negativecharges are trapped to the silicon nitride film, the negative chargesmay sometimes form a depletion layer below the field oxide film FOX.Such depletion layer may possibly fluctuate characteristics of thesemiconductor device SD. On the contrary, in this embodiment, asubstantially uniform electric field is generated by the metalinterconnect MW. In this case, the electric field caused by the negativecharges can be moderated by the electric field of the metal interconnectMW. Thus, fluctuation of the characteristics of the semiconductor deviceSD can be suppressed.

Further, according to this embodiment, the metal interconnect MW isformed of a high resistance metal. Accordingly, less current flows inthe metal interconnect MW. Thus, a current flowing by way of the metalinterconnect MW from the high voltage side (on the side of the drainregion DRR) to the low voltage side (on the side of the source regionSOR) by way of the metal interconnect MW can be restricted.

Further, according to this embodiment, the metal interconnect MW isformed by using the barrier metal film BM (barrier metal films BM1 andBM2) (for example, as illustrated in FIG. 10). Accordingly, in thisembodiment, the metal interconnect MW can be formed efficiently.

Second Embodiment

FIG. 12 is a cross sectional view illustrating a configuration of asemiconductor device SD according to a second embodiment, andcorresponds to FIG. 2 for the first embodiment. The semiconductor deviceSD according to this embodiment has a configuration similar to that ofthe semiconductor devices SD according to the first embodiment exceptfor the followings.

In this embodiment, like the first embodiment, the metal electrode ME1is situated on the side of the second region RG2 in contrast to themetal interconnect MW, and covers the interlayer dielectric film ILD. Onthe other hand, the metal electrode ME2 is situated on the side of thefirst region RG1 in contrast to the metal interconnect MW and covers theinterlayer dielectric film ILD. The metal electrode ME1 is covered withan anti-reflection film ARC1. Also, the metal electrode ME2 is coveredwith an anti-reflection film ARC2. As will be described specificallylatter, the anti-reflection films ARC1 and ARC2 are metal films forpreventing occurrence of halation upon lithography for forming the metalelectrodes ME1 and ME2. The metal interconnect MW is formed of amaterial identical with that of the anti-reflection films ARC1 and ARC2.The anti-reflection films ARC1 and ARC2 are covered by a protection filmPL and a cover film CL.

FIG. 13 to FIG. 16 are cross sectional views illustrating a method ofmanufacturing the semiconductor device SD illustrated in FIG. 12. First,steps illustrated in FIG. 3 to FIG. 8 are performed in the same manneras in the first embodiment.

Then, as illustrated in FIG. 13, the metal film ME and the barrier metalfilm BM are patterned, thereby forming an opening OP in the metal filmME and the barrier metal film BM over the field oxide film FOX. Thus,the metal film ME forms a metal electrode ME1 on the side of the firstregion RG1 in contrast to the opening OP in a plan view and forms ametal electrode ME2 on the side of the second region RG2 in contrast tothe opening OP in the plan view. On the other hand, the barrier metalfilm BM forms a barrier metal film BM1 on the side of the first regionRG1 in contrast to the opening OP in the plan view and forms a barriermetal film BM2 on the side of the second region RG2 in contrast to theopening OP in the plan view.

Then, as illustrated in FIG. 14, an anti-reflection film ARC is formed,for example, by sputtering. Thus, the anti-reflection film ARC is formedalong the bottom and the lateral sides of the opening OP and the uppersurface of the metal electrodes ME1 and ME2. The thickness of theanti-reflection film ARC is substantially identical in any of theregions. As will be described specifically later, the anti-reflectionfilm ARC is a metal film that forms a metal interconnect MW. In thisembodiment, the anti-reflection film ARC comprises titanium nitride(TiN). However, the material of the anti-reflection film ARC is notrestricted to titanium nitride.

Then, as illustrated in FIG. 15, the anti-reflection film ARC ispatterned. Thus, a metal interconnect MW is formed inside of the openingOP in a plan view and, concurrently, anti-reflection films ARC1 and ARC2are formed over the metal electrodes ME1 and ME2 respectively. When thethickness of the anti-reflection film ARC is substantially identical inany of the regions, the thickness of the metal interconnect MW issubstantially identical with that of the anti-reflection films ARC1 andARC2. Halation may sometimes occur by the reflection of light at themetal electrodes ME1 and ME2 in lithography for forming the metalinterconnect MW. The anti-reflection film ARC (anti-reflection filmsARC1, and ARC2) functions as a metal film for suppressing such halation.

Then, as illustrated in FIG. 16, a protection film PL and a cover filmCL are stacked in this order over the anti-reflection films ARC1 andARC2 and over the metal interconnect MW. Thus, the semiconductor deviceSD illustrated in FIG. 12 is manufactured.

As described above, according to this embodiment, an electric fieldbetween the high voltage side (on the side of the drain region DRR) andthe low voltage side (on the side of the source region SOR) can bemoderated by the metal interconnect MW. Further, according to thisembodiment, the metal interconnect MW is formed by using theanti-reflection film ARC (anti-reflection films ARC1 and ARC2) (forexample, as illustrated in FIG. 15). Accordingly, the metal interconnectMW can be formed efficiently in this embodiment.

Modified Embodiment

FIG. 17 is a plan view illustrating the configuration of a semiconductordevice SD according to a modified embodiment. In the embodimentillustrated in the drawing, a field oxide film FOX has a planar shapehaving a protrusion CON protruding from one side of a rectangle. Anelectrode pad EP is arranged over the protrusion portion CON. Further,an interconnect WR is formed over the field oxide film FOX. Theinterconnect WR extends from a first region RG1 to a second region RG2.The interconnect WR electrically connects the electrode pad EP and thedrain electrode DRR (for example, illustrated in FIG. 2 of FIG. 12).That is, a driving voltage for the drain region DRR is applied to theelectrode pad EP.

The interconnect WR is formed, for example, of a material identical withthat of the metal electrodes ME1 and ME2 (for example, the metal film MEillustrated in FIG. 9 or FIG. 13). That is, the interconnect WR isformed concurrently with the metal electrodes ME1 and ME2 by using themetal film ME (for example, as illustrated in FIG. 9 or FIG. 13).Further, a barrier metal film BM is situated below the interconnect WR(for example, as in FIG. 9), or an anti-reflection film ARC is situatedover the interconnect WR (for example, as illustrated in FIG. 13).

When the interconnect WR is situated over the field oxide film FOX asdescribed above, the metal interconnect MW cannot be provided in aregion overlapping the interconnect WR in a plan view. In this case, asillustrated in the drawing, the metal interconnect MW can be repeatedlyprovided while being turned back so as not to overlap the interconnectWR in the plan view. Also in this case, an electric field between thehigh voltage side (on the side of the first region RG1) and the lowvoltage side (on the side of the second region RG2) can be madesubstantially uniform in the same manner as in the first embodiment orin the second embodiment.

Further, in the embodiment illustrated in the drawing, a withstandvoltage between the first region RG1 (high voltage region) and thesecond region RG2 (low voltage region) is made high by the field oxidefilm FOX and the metal interconnect MW. Accordingly, a memory region MRand a logic region LR can be arranged in a region adjacent with thefield oxide film FOX in a plan view. More specifically, in theembodiment illustrated in the drawing, the planar configuration of thefield oxide film FOX has a rectangular shape having a protrusion CONdescribed above on one side. Then, a memory region MR and a logic regionLR are formed along the sides of the field oxide film FOX different fromthe one side described above. Even when the memory region MR and thelogic region LR are arranged near the high voltage region (first regionRG1), the memory region MR and the logic region LR are protected againstthe high voltage by the field oxide film FOX and the metal interconnectMW.

Examples of reference embodiments are to be described additionally.

1. A method of manufacturing a semiconductor device including the stepof:

forming a field insulation film over a substrate thereby forming a firstregion surrounded by the field insulation film in a plan view, a secondregion situated outside the first region by way of the field insulationfilm in a plan view,

forming a drain region of a transistor in the first region and,concurrently, forming a source region of the transistor in the secondregion,

forming an interlayer dielectric film covering the substrate, the fieldinsulation film, and the transistor,

forming a barrier metal film over the interlayer dielectric film,

forming a metal film over the barrier metal film,

forming an opening in the metal film over the field insulation film,

patterning the barrier metal film situated inside the opening in theplan view, thereby forming a metal interconnect repeatedly providedbeing turned back or spirally in the direction along the edges of thefirst region.

2. A method of manufacturing a semiconductor device including the stepsof:

forming a field insulation film to a substrate, thereby forming a firstregion surrounded by the field insulation film in a plan view and asecond region situated outside the first region by way of the fieldinsulation film in the plan view,

forming a drain region of a transistor in the first region and,concurrently, forming a source region of the transistor in the secondregion,

forming an interlayer dielectric film covering the substrate, the fieldinsulation film, and the transistor, in the second region,

forming a metal film over the interlayer dielectric film,

forming an opening in the metal film over the field insulation film,

forming an anti-reflection film which is a metal film covering the metalfilm and the interlayer dielectric film situated inside the opening inthe plan view, and

patterning the anti-reflection film situated inside the opening in theplan view, thereby forming a metal interconnect repeatedly providedbeing turned back or spirally in the direction along the edges of thefirst region.

The inventions made by the present inventors have been describedspecifically with reference to the preferred embodiments but it will beapparent to a person skilled in the art that the present invention isnot restricted to the preferred embodiments described above but can bemodified variously within a range not departing the gist of theinvention.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a transistor formed in the semiconductorsubstrate; a first region formed in the semiconductor substrate andincluding a drain region of the transistor; a second region formed inthe semiconductor substrate and including a source region of thetransistor; a field insulation film formed in the semiconductorsubstrate, formed between the first region and the second region andsurrounding the first region in a plan view; and a first interconnectformed over the field insulation film, wherein the field insulating filmincludes a silicon oxide film, wherein the first interconnect isrepeatedly provided while being turned back or in a spiral shape in thedirection along the edges of the first region, and formed of titanium,titanium nitride, tantalum or tantalum nitride, wherein the innermostcircumference of the first inter connect is electrically connected withthe drain region, and wherein the outermost circumference of the firstinter connect is electrically connected with the source region or aground potential.
 2. A semiconductor device according to the claim 1,further comprising: a second interconnect formed over the fieldinsulation film and extending from the first region to the secondregion, wherein, in a plan view, the first and second interconnects donot overlap each other.
 3. A semiconductor device according to the claim2, further including: an electrode pad formed over the field insulationfilm, wherein the second interconnect is electrically connected with theelectrode pad and the drain region.